Cross Reference to Related Patent Applications
The present patent application is related to two pending patent applications entitled "Compressive Pedestal for Microminiature Connections" (Ser. No. 811,560, Filed: Dec. 20, 1985) and "Chip Interface Mesa" (Ser. No. 811,239, Filed: Dec. 20, 1985), both also invented by Nils E. Patraw and both assigned to the Hughes Aircraft Company.
1. Field of the Invention
The present invention pertains to Ultra-Dense, Extremely Large Scale Integration and wafer scale synthesis of microelectronic components residing on a large number of integrated circuits. The specific focus of the preferred embodiment is the planar and orthogonal space optimization of active microelectronic circuit elements which makes possible multi-chip VHSIC hybrids having extraordinarily high signal processing capabilities and enoromous memory capacity.
2. Background Information
Over the past four decades, the electronics industry has witnessed vast improvements in the performance of electronic components. The transition from thermo-ionic devices to solid state diodes and transistors was the first phase of intense efforts to miniaturize circuitry in order to construct powerful digital computers. The second great phase of innovation involved the consolidation of discrete solid state devices into a compact, unitary circuit which shared a single housing. Before the advent of integrated circuits, components like transistors were individually encapsulated in plastic cases or resided separately in metal cans. These single elements were generally mounted on circuit boards and each had a number of leads connected together by soldered wires. The first generation of integrated circuits combined many discrete active elements together on several alternating layers of metallic and dielectric films which were deposited on an insulating substrate. These early integrated circuits, called thin-film hybrids, were the precursors of current integrated circuits which contain a solitary, but extremely powerful and densely packed, semiconductor chip or die. This semiconductor chip comprises a base or substrate of material, upon which many thin layers are formed that are, in turn, coupled together by tiny, metallic interconnects or vias which pass vertically through the several horizontal layers. A semiconductive material such as silicon, germanium, or gallium arsenide can be chemically altered in order to form carefully selected, minute regions having different electrical properties. These distinct regions are now fabricated with great precision, and each region may measure less than one millionth of an inch. A few regions which exhibit different degrees of electrical conductivity can be grouped together in order to form a device that can help perform a mathematical calculation or store information. These groups of microscopically small regions or zones within one of the many layers of one monolithic chip are the modern analogs to the discretely packaged components which preceded them twenty and thirty years ago.
As each phase of electronic components produced improvements in calculation speed and memory capacity, the packaging of these components became more and more important. Technological advancements that solve problems concerning the fabrication or further miniaturization of semiconductor materials and devices simultaneously create a concomitant packaging problem. As circuit components shrink to increasingly smaller dimensions, the problem of accessing each component grows worse. When integrated circuits become so densely packed that a million of separate active devices occupy a space smaller than the diameter of the eraser on a common pencil, the difficulties involved in exchanging information in the form of electrical signals between that vast network of tiny circuit elements and the outside world become enormous.
Another level of complication is reached when designers attempt to connect many integrated circuits together in a unitary system. Semiconductor chips which are shorter than the width of the eraser at the end of the pencil and less than two one hundreths of an inch thick are manufacturer simultaneously by the hundreds on thin circular wafers of semiconductive material that are typically about four inches wide. Recent attempts to couple all the separate chips on the wafer gave rise to the term wafer scale integration. An electronic device which could incorporate tens, hundreds, or perhaps even thousands or millions of already immensely powerful separate chips, each comprising roughly a million active components, together on one wafer would constitute a tremendous technological leap forward in the electronics arts.
Among the most serious problems encountered in designing and manufacturing integrated circuits and multiple integrated circuit arrays are the deleterious consequences of using fine filaments of wire to connect the miniscule terminals or pads which are the access points to the outside world from the internal circuitry of the integrated circuit. These fragile, very light gauge connecting wires are typically one one-thousanth of an inch in diameter. One common technique for attaching these wires or leads to the conductive external terminals of the chip is thermocompression bonding. This process combines the application of heat and stress on an integrated circuit die. A very small wedge-shaped probe or tool called a bonding wedge must be viewed through a microscope and guided over a wire which is to bonded onto a conductive pad. The pad is usually located at the periphery of the semiconductor chip or die, which is placed on a heating device in order to soften the metallic material comprising the pad. A refinement of the bonding wedge is called a nailhead or ball bonder, in which the pressure bonding tool consists of a glass capillary tube that feeds the wire through its center to the pad. A flame melts the end of the wire that protrudes out of the open end of the capillary tube and forms a ball having a diameter about twice the thickness of the wire. The wire is then retracted in the tube and the ball is held snugly against the orifice while the tube is moved over the pad and impressed upon it with considerable force. The compression deforms the ball into a flattened thermocompression bond shaped like the head of a nail. The tube is then pulled back from the pad, and the flame is employed again to melt the wire which is now attached to a pad on the die. The wires and the contact pads are typically made of gold or aluminum.
Although thermocompression bonding has proven useful over many years of manufacturing, this method suffers from many shortcomings. Aside from the great expense incurred in either bonding wires and pads manually or with the aid of costly automated equipment, any mechanical connection like a pressure bond is susceptible to failure caused by a multitude of environmental factors. Since any fabrication process will be less than perfect, some wirebonds will be faulty after manufacturing. Even if only one percent of the connections are inadequate, the entire electronic system which includes the chip with the bad connection may be rendered completely inoperative as a consequence. Different rates of expansion and contraction of the connected materials due to changes in temperature will tend to destroy bonds over time. The ambient environment may contain compounds which will initiate chemical processes such as oxidation that may corrode and destroy metallic connections. The installation of subcomponents, handling, or vibration encountered during use may detach these wire bridges in time.
In addition to the nettlesome problems of keeping a wire bond intact over the life of an electronic device, this mode of connecting portions of one chip or an array of many chips is beset by problems even if all the bonds are perfectly made and are never broken. The vast number of wire bonds needed to connect large numbers of chips result in an enormous total length of conductive pathways in the system circuit. These conductors consume electrical power since they are resistive components. Increased ambient temperature caused by this thermal heating may impair the operation of the associated integrated circuits. The wires inject unwanted inductance and capacitance into otherwise precisely balanced circuits. Crosstalk between conductors may severely impair the performance of the entire system. Time delays inherent in the long pathways reduce computation capability.
Perhaps the worst problem is the enormous space which is wasted when wires are used to connect together portions of a chip or an array of many chips. Each span of wire that connects two points which reside substantially in the same plane requires a looped, generally parabolic length of bent wire. The amount by which the wire can be bent is limited by the fragility and susceptibility of the wire to fracture. In addition, the size of the wire bonding tool mandates a minimum spacing between contact points which receive thermocompression bonds. These loops of wire impose limits on the horizontal density of the chip deployment, since a minimum space for each loop must be provided between each adjacent chip. Conventional wire bonding techniques impose die interspacing contraints of no less than twice the thickness of the die. If the die is on the order of twenty mils of an inch in height, as much as fifty mils will be wasted in order to provide adequate separation for the making the wire bonds. The pads which receive the wire bonds also consume precious space on the die. Each pad must be large and sturdy enough to tolerate the great pressure transmitted by the wire bond tool. The wire bonds not only consume valuable horizontal surface area on the face of the die, but also take up space above the plane of the die. The looped portions of the connecting wires can extend far above the die face and preclude the stacking of several levels of chip array planes. When connecting wires consume space above or below the active die surface, the vertical or orthogonal space that extends perpendicular to the active circuitry must be reserved for protruding wires. These exposed wires are vulnerable to a host of environmental hazards including physical shock, vibration, and extremes of temperature.
Previous microcircuit connection and wafer scale integration inventions have attempted to solve the depolyment and packaging problems inherent in combining and connecting millions of active circuit components using a variety of approaches. In U.S. Pat. No. 3,811,186, Larnerd et al. describe a method for aligning and supporting microcircuit devices on substrate conductors when the conductors are attached to the substrate. A shaped, flexible, insulative material placed between the devices and their corresponding conductors supports terminals which can be fused together with heat in order to attach conductors after they have been properly aligned.
Beavitt et al. disclose an integrated circuit package including a number of conductors bonded between a cover and a cavity formed within a base that holds a chip in U.S. Pat. No. 3,825,801. This cavity serves as a carrier for the chip, which is held in place between conductive strips of resilient material that are secured between a base and cover of insulating material.
A process for producing sets of small ceramic devices such as leadless inverted chip carriers that have solderable external connections is disclosed by Hargis in U.S. Pat. No. 3,864,810. After firing several layers of ceramic material on a base sheet, Hargis mounts a chip on the ceramic carrier by embedding or encapsulating it in an epoxy resin in order to provide leads for the chip which are more easily connected to external devices than the chip terminals themselves.
In U.S. Pat. No. 3,868,724, Perrino reveals connecting structures for integrated circuit chips which are fabricated by forming many sets of leads on a flexible tape. These leads penetrate through holes formed in the tape and terminate in contacts which are arranged in a pattern that corresponds to a pattern of contacts on an integrated circuit chip. The chips are enclosed by an epoxy encapsulant after they are bonded to the contacts.
Hartleroad et al. explain a method and apparatus for positioning semiconductor flip chips onto one end of a transfer probe which automatically and magnetically aligns the chips and bonds them to an overlying lead frame structure. Their method for placing flip chips into one end of an elongated groove of a positioning apparatus and conveying them on guide rails using a magnetic force to properly locate the chips before bonding is the subject of U.S. Pat. No. 3,937,386.
An electrical package for Large Scale Integrated devices which utilizes solder technology to interconnect a carrier, a circuit transposer and LSI devices is described by Honn et al. in U.S. Pat. No. 4,074,342. The Honn electrical package includes a carrier which has a thermal expansion coefficient similar to semiconductor material, a standard array of terminal pins, and the transposer, which they claim eliminates mechanical stress on solder joints that is caused by dissimilar thermal expansion of the various packaging materials.
Inoue discloses a semiconductor device insulation method in U.S. Pat. No. 4,143,456. This invention employs a protective covering for a semiconductor device which includes a circuit board bearing a conductive pattern and a chip. Inoue fixes his chip with a eutectic or electrically connected adhesive to a die bonded portion of the circuit board pattern with aluminum wire.
U.S. Pat. No. 4,147,889--Andrews et al. describe a thin, dielectric, dish-shaped chip carrier which has flexible mounting flanges having plated or bonded solderable conductive traces and paths. These traces and paths are coupled with plated or bonded heat sinks which are electrically grounded and provide structural integrity.
A flat package for an integrated circuit device that has output pads comprising a supporting member for the integrated circuit device, external output terminals, and array of output conductors, and an electrically insulating encapsulation cover is illustrated in Ugon's U.S. Pat. No. 4,264,917. This invention includes contact islands arranged on a supporting wafer to provide a package for one or more integrated circuit devices having a reduced thickness and surface area.
None of the inventions described above solves the problem of wasted planar and orthogonal space that results from the high portion of chip assemblies that are devoted to chip interconnections such as wirebonds. None of these prior methods or apparatus provides an effective and comprehensive solution which addresses all of the complex aspects of achieving ultra-high density of active semiconductor components. Such a solution to this problem would satisfy a long felt need experience by the semiconductor and intergrated circuit industries for over three decades.
A truly practical and reliable means for producing efficacious intra-chip and chip-to-chip interconnections without squandering a substantial portion of the die's planar and orthogonal space would constitute a major advancement in the microelectronics field. Manufacturers of semiconductor dies could employ such an innovative design to produce integrated circuits capable of processing information at speeds greatly exceeding the current state of the art and capable of storing vast quantities of data far beyond today's most densely packed designs. Such an invention would ideally be suited to operate in cooperation with a wide variety of computing systems and would perform consistently and reliably over a wide range of operating conditions and system applications. Extremely Large Scale Integration microcircuitry would also satisfy the rigorous demands of supercomputers and orbital defense systems. An invention which enables aerospace microelectronic designers to deploy enormously powerful yet extremely compact integrated circuits in orbit for space defense systems would most certainly constitute a major technological advancement in the electronics arts.